Wednesday, April 10, 2013

ARM hiring fresher “Design Engineer” for BE/BTech/ME/MTech graduates, April 2013, Bangalore




Company Name:  ARM



Company Website:  www.arm.com

Job Details:

Requirement: Design Engineer

Location: 
Bangalore

Category: IT/Software

Experience: (0 - 2) Years

Package: As per the industry standards

Job ID: 3083
.


Description:

 ARM offers IC designers a wide range of choices from its broad portfolio of Physical IP library products. The ARM high-performance, high-density, low-power and ultra low-power libraries are optimized for each silicon technology. ARM's Process-Perfect Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM Physical IP products have been used in circuits running as fast as 1 GHz and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 32nm, 28nm, 20nm and 14nm semiconductor process technology nodes for various foundries and IDMs for bulk CMOS and SOI process

Desired Qualification:
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Degree: BE/BTech/ME/MTech Graduates

Other Skills Required:

  1. The candidate must be a BE/BTech/ME/MTech graduate from any recognized university
  2. Good knowledge in any physical verification tools like Calibre, Hercules, Assura
  3. Experience in Extraction tools like Mentor XRC or Synopsys Star RC
  4. Good knowledge in Synopsys HSpice, Cadence  Spectre
  5. Basic understanding of SRAM, IO's and Standard cell design
  6. Perl/tcl, skill programming experience
  7. PTG is the central group, which constantly interacts with the product groups, layout groups, and project management. Some of the responsibilities are:
  8. Implementation of all the foundry specific physical verification flows like DRC, LVS
  9. In addition to these PTG will implement ARM version of the Checks to maintain uniform quality of layouts across the foundries.
  10. Inspection and evaluation of all process receivables from foundries
  11. Implementation of cell level extraction and chip level extraction flows
  12. Implementation of the spice decks and QA
  13. Constant design support to the product groups
  14. Constant interaction with the Design Automation to improve/enhance the flows
  15. Support for the product migration from one technology to another technology, study of impact of new design rules/spice models on the existing designs.
  16. Test chip Mask data analysis/inspection prior to the fabrication.
  17. Consultation on device physics, process technology etc
                                                                                              
To Apply: Click here...

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